The present invention relates to a method and apparatus for semiconductor device production process monitoring (or, a “semiconductor device production process monitoring apparatus and method,” hereafter) for performing evaluation and management of a circuit pattern in a semiconductor device production process; and also relates to a method and apparatus for estimating a cross-sectional shape of a pattern. More specifically, the present invention relates to a technique effective for pattern cross-sectional shape management by a length-measurement or metrological SEM (scanning electron microscope), process condition management, and device characteristics management.
Conventionally, the device characteristics of transistors are primarily dependent on the gate wireline width (gate length), and in the semiconductor device production process, the pattern line width is measured and controlled by using a metrological SEM (scanning electron microscope/microscopy). However, with recent rapid progress in the miniaturization of semiconductor circuit patterns, the transistor channel lengths become smaller, such that, as factors determining the device characteristics, not only the wire line width, but also the cross-sectional shape significantly affects the pattern. The following describes the management of the patterns of semiconductor devices in semiconductor production steps.
FIGS. 1A to 1J show examples of normal and abnormal cross-sectional shapes of semiconductor devices. FIG. 1A shows an example of a cross-sectional shape generally considered to be most desirable among patterns of semiconductor devices being formed. In this case, the tilt angle of the respective pattern sidewall is substantially vertical. In addition, the sidewall is substantially perpendicular to a base plane in a pattern bottom portion 102, and a pattern upper plane and the pattern sidewall are substantially perpendicular to one another in a pattern upper portion 101. In comparison, FIGS. 1B to 1J, respectively, show examples of patterns that, among patterns of semiconductor devices, are generally classified as abnormal shapes and that can cause cases in which desired device characteristics cannot be obtained. However, depending on the case, pattern shapes such as shown in FIGS. 1B to 1J are intentionally formed to form desired circuits.
More specifically, FIG. 1B is a pattern in which the tilt angle of the pattern sidewall is less than 90 degrees. Such a pattern shape is referred to as an “ordinary taper” shape (pattern). FIG. 1C is a pattern in which the tilt angle of the pattern sidewall is greater than 90 degrees. Such a pattern shape is referred to as a “backward taper” shape (pattern). FIG. 1D is a pattern of a shape in which a pattern central portion is narrow, and the pattern sidewall is bowed inward. Such a pattern shape is referred to as a “bowing” shape (pattern). FIG. 1E is a pattern of which corner shapes in the pattern upper portion are rounded. Such a pattern shape is referred to as a “top-rounding” shape (pattern). FIG. 1F is a pattern having a shape in which the corner portions overhang. Such a pattern shape is referred to as an “overhang” shape (pattern). FIG. 1G is a pattern having a shape in which feet in a pattern bottom portion are trailed such as to form a skirt. Such a pattern shape is referred to as a “skirt-trailed” shape (pattern). FIG. 1H is a pattern having a shape in which sidewall portions coming to cross with the lower-base face are bent inwardly of the sidewalls in the pattern upper portion. Such a pattern shape is referred to as a “notch” shape (pattern). FIG. 1I shows patterns having a shape in which the pattern height is less than a desired pattern height. Such a pattern is referred to as a “film-reduced pattern.” FIG. 1J shows two patterns, one having a pattern width is greater than a desired pattern width, and the other having a pattern width less than the desired pattern width.
The shapes of FIGS. 1A to 1J are examples of abnormal shapes occurring with inappropriate conditions of the semiconductor device production process. In a circuit pattern of a semiconductor device, the gate length coincident with the dimension of the pattern bottom portion, such that it is important to measure the dimension of the bottom portion. However, in a gate forming process, ions are implanted with the wireline pattern being used as a mask, thereby forming the source and drain of the transistor. As such, the tilt of the pattern sidewall, the shape of the pattern bottom portion, and the like affect the process result of the step of ion implantation, thereby resulting in variations in the device characteristics, such that it is important to manage the cross-sectional shape of the gate pattern.
Further, in the exposure process, the pattern is transferred onto the resist by using the exposure mask, and performs development based on the transferred pattern, thereby to form a resist pattern. A ground film is etched in a subsequent etching process with a subsequently formed resist pattern being used as a mask pattern. As such, in the event that abnormality exists in the cross-sectional shape of the resist pattern, abnormality can be potentially induced in the etching pattern of the ground film in the subsequent step of etching. Thus, cross-sectional shape evaluation is very important in either the gate forming or exposure process. A technique similar to the conventional technique described above is disclosed in Japanese Unexamined Patent Application Publication No. 10-125749, for example.